Abstract

Automatic target recognition (ATR) in synthetic aperture radar (SAR) imagery often requires billions of operations per second. This paper describes a compact scalable system developed at Myricom for high-performance implementation of the template-based SAR ATR algorithms developed by Sandia National Laboratories. The Myricom system is mapped on the multiple concurrent field programmable array (FPGA) computing nodes connected by Myrinet. These FPGA nodes achieve high efficiency, through the exploitation of the unique characteristics of the ATR algorithm in FPGA. The contributions of this paper are the descriptions of the architectural designs for the ATR system on the scalable FPGA nodes.

Date

October 29, 2000

Authors

Young H Cho

Conference

Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No. 00CH37154)

Volume

2

Pages

1545-1549

Publisher

IEEE