Abstract

A method for assuring that integrated circuits are free of malicious circuit insertions and/or IC design modifications through mask swapping/addition is provided. The method includes a step of comparing 3D tomographic images constructed from design GDS to the 3D tomographic images constructed from in-line fab metrology data.

Date

January 14, 2025

Authors

AP Jacob, J Damoulakis, A Jaiswal, DK Shenoy, A Rittenbach

Inventors

Ajey Poovannummoottil Jacob, John Damoulakis, Akhilesh Jaiswal, Devanand Krishna Shenoy, Andrew Rittenbach

Patent_office

US

Patent_number

12198325

Application_number

17244183