Abstract

Designing hardware cores for FPGAs can quickly become a complicated task, difficult even for experienced engineers. With the addition of more sophisticated development tools and maturing high‐level language‐to‐gates techniques, designs can be rapidly assembled; however, when the design is evaluated on the FPGA, the performance may not be what was expected. Therefore, an engineer may need to augment the design to include performance monitors to better understand the bottlenecks in the system or to aid in the debugging of the design. Unfortunately, identifying what to monitor and adding the infrastructure to retrieve the monitored data can be a challenging and time‐consuming task. Our work alleviates this effort. We present the Hardware Performance Monitoring Infrastructure (HwPMI), which includes a collection of software tools and hardware cores that can be used to profile the current design …

Date

March 15, 2026

Authors

Andrew G Schmidt, Neil Steiner, Matthew French, Ron Sass

Journal

International Journal of Reconfigurable Computing

Volume

2012

Issue

1

Pages

162404

Publisher

Hindawi Publishing Corporation