Abstract

The traditional von Neumann architecture faces significant challenges, leading to increased latency and energy consumption due to data transfers and bandwidth limitations between processing and memory units. To address this, we propose a novel scalable in-memory optical compute processor chip that integrates processing directly within a high-speed (⪆ 20 GHz) photonic SRAM, eliminating separate units for enhanced efficiency. Our design combines the speed of optical analog computing (2N/2 -level, N/2-bit input) with the control of a N/2- bit digital memory, delivering high-fidelity N-bit output in every cycle using a single wavelength channel. This system is scalable to multiple wavelength channels using dense wavelength division multiplexing for hyperspectral encoding, enabling massive parallelism. By performing computations within the memory, our scalable optical in-memory compute processor …

Date

March 19, 2025

Authors

Sugeet Sunder, Md Abdullah-Al Kaiser, Sasindu Wijeratne, Clynn J Mathew, Viktor Prasanna, Akhilesh Jaiswal, Ajey Jacob

Conference

Smart Photonic and Optoelectronic Integrated Circuits 2025

Volume

13370

Pages

107-113

Publisher

SPIE