Abstract

Academic packing algorithms have typically been limited to theoretical architectures. In this paper, we describe RSVPack, a packing algorithm built on top of RapidSmith to target the Xilinx Virtex 6 architecture. We integrate our packer into the Xilinx ISE CAD flow and demonstrate our packer tool by packing a set of benchmark circuits and performing routing and timing analysis inside ISE.

Date

November 30, 2016

Authors

Travis Haroldsen, Brent Nelson, Brad Hutchings

Conference

2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

Pages

1-6

Publisher

IEEE